The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop (DLL) circuit of a semiconductor memory device.
A system is implemented with a variety of semiconductor devices. One of them is a semiconductor memory device used as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by addresses inputted together with the data.
As the operating speed of the system increases, the data processor requires the semiconductor memory device to input/output data at higher speed. As semiconductor integrated circuit (IC) technologies rapidly develop, the operating speed of the data processor increases, but the data input/output speed of the semiconductor memory device does not keep up with the increased operating speed of the data processor.
Many attempts have been made to develop semiconductor memory devices that can increase data input/output speed up to the level required by the data processor. One of these semiconductor memory devices is a synchronous memory device that outputs data at each period of a system clock. Specifically, the synchronous memory device outputs or receives data to or from the data processor in synchronization with the system clock. However, because even the synchronous memory device could not keep up with the operating speed of the data processor, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or receives data at each transition of the system clock. That is, the DDR synchronous memory device outputs or receives data in synchronization with falling edges and rising edges of the system clock.
However, a system clock inevitably has a delay time until it arrives at a data output circuit because it passes through a clock input buffer, a clock transmission line, etc. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock.
To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit compensates for the delay caused by internal circuits of the semiconductor memory device until the system clock inputted to the semiconductor memory device is transferred to the data output circuit. The DLL circuit finds the delay time of the system clock, which is caused by the clock input buffer, the clock transmission line, etc. of the semiconductor memory device. Then, the DLL circuit delays the system clock by the found delay time and outputs the delayed system clock to the data output circuit. That is, the DLL circuit outputs a delayed-locked clock (DLL clock) to the data output circuit. The data output circuit outputs data in synchronization with the DLL clock. Therefore, the data are correctly outputted to the external circuit in synchronization with the system clock.
In an actual operation, the DLL clock is transferred to the output buffer at a time point earlier by one period than a time point when the data must be outputted, and the output buffer outputs data in synchronization with the received DLL clock. Therefore, the data is outputted faster than the delay of the system clock caused by the internal circuit of the semiconductor memory device. In this way, the data are correctly outputted in synchronization with the rising and falling edges of the system clock inputted to the semiconductor memory device. That is, the DLL circuit is a circuit to find how fast the data must be outputted in order to compensate for the delay of the system clock within the semiconductor memory device.
Recently, a DLL circuit is designed to generate DLL clocks with different phases. As the data I/O speed becomes faster, the DLL circuit generates DLL clocks with different phases in order to maximumly secure a timing necessary to process a plurality of data. A data I/O circuit aligns data using the DLL clocks with different phases. AT this point, a delay skew occurs between the DLL clocks. When data are outputted at a high speed, even a small delay skew will cause a serious data I/O error.